Active matrix-type display devices provided with thin film transistors (hereinafter referred to as “TFTs”) as switching elements for pixels, which have fast response speeds and readily provide display with multilevel grayscale, have been used in a wide variety of devices including a television set, a mobile phone, a portable game machine, and a vehicle-mounted navigation system.
In a typical active matrix-type display device, a TFT array substrate and a counter substrate are opposed to each other, and a display element (liquid crystal, organic electroluminescence, etc.) is sealed with a sealing material between the TFT array substrate and the counter substrate.
(TFT Array Substrate)
The following will describe the configuration of a TFT array substrate with reference to FIG. 12.
FIG. 12 is a plan view schematically showing the configuration of an essential part of the TFT array substrate.
As shown in FIG. 12, a TFT array substrate 20 has a display area 22 formed in a central part thereof, and display-driving-use TFT elements (switching elements) (not shown) for driving pixel electrodes are formed in a matrix manner in the display area 22.
As to the display-driving-use TFT element, a gate electrode is connected to a gate line 42, a source electrode is connected to a source line 44, and a drain electrode is connected to a pixel electrode (not shown).
The gate lines 42 and the source lines 44 are provided in directions orthogonal to each other on the TFT array substrate 20. Note that the gate lines 42 and the source lines 44 are provided in different layers disposed on the TFT array substrate 20 through an insulating layer interposed therebetween, so that the gate lines 42 and the source lines are not electrically connected to each other at intersection thereof.
In an area surrounding the display area 22, i.e. in an area near a substrate end side 26 of the TFT array substrate 20, a surrounding area 24 is formed. On right and left ends of the surrounding area 24 (in a direction indicated by an arrow X in FIG. 12), a gate driving circuit 60 is provided.
The gate driving circuit 60 is electrically connected to the gate lines 42 and applies gate signals to the gate lines 42.
The gate driving circuit 60 is provided on the right and left ends of the surrounding area 24. Therefore, in cases where each of the gate lines 42 receives signals from its both ends, it is possible to reduce waveform distortion of the signals. This makes it possible to downsize a plurality of TFT elements (driving elements) making up the gate driving circuit 60, thus providing a liquid crystal display panel 10 having a narrow picture frame.
Further, even in cases where each of the gate lines 42 receives signals only from one end, sizes of right and left picture frame regions of the liquid crystal display panel 10 can be made equal by separating the gate lines 42 into (a) a group of the gate lines 42 that are driven by the right-side gate driving circuit 60 and (b) a group of the gate lines 42 that are driven by the left-side gate driving circuit.
Meanwhile, on one end of upper and lower ends of the surrounding area 24 (in a direction indicated by an arrow Y in FIG. 12), a driver 62 is provided.
The driver 62 is electrically connected to the source lines 44 and applies source signals to the source lines 44.
Further, both of the gate driving circuits 60 are electrically connected respectively to gate driving circuit lines which comprise a clock line and other lines. To the gate driving circuit lines, signals necessary for operation of the gate driving circuit 60 are supplied from a DC/DC converter and a display control circuit, which are located outside the TFT array substrate 20, through FPCs (Flexible Printed Circuits) or the like.
Note that the gate driving circuit lines (not shown) of the right-side gate driving circuit 60 and the gate driving circuit lines 46 of the left-side gate driving circuit 60 are interconnected through lines 64, for example, on a side of the display area 22 opposite to the side thereof on which the driver 62 is provided.
The interconnection between both of the gate driving circuit lines eliminates the need for supply of signals to both the gate driving circuit lines (not shown) of the right-side gate driving circuit 60 and the gate driving circuit lines 46 of the left-side gate driving circuit 60 through the FPC. Therefore, it is possible to form the FPC with a narrow width and to thus reduce cost of the FPCs. Note that as shown in FIG. 12, it is preferable that the lines 64 are configured not to interconnect with the source lines 44 in terms of the effect of reducing a signal load.
In FIG. 12, the gate driving circuits 60 are provided on both sides of the display area 22. Alternatively, the gate driving circuit 60 may be provided on one side of the display area 22. Further, the signals supplied to the gate driving circuit lines 46 may be fed from the driver 62.
The TFT array substrate 20 and the counter substrate (not shown) are bonded together through a seal 90, which makes up the liquid crystal display panel 10. The seal 90 is provided in picture frame shape in an inner area of the TFT array substrate 20 along the substrate end side 26 of the TFT array substrate 20.
(Patent Literature 1)
A specific configuration of the gate driving circuit 60 is, for example, the configuration described in Patent Literature 1.
FIG. 13 is a block diagram schematically showing the configuration of gate driving circuit 60 described in Patent Literature 1.
As shown in FIG. 13, in the surrounding area 24, the gate driving circuit lines 46 connected to the gate driving circuit 60 and the FPC (not shown) are provided.
The gate driving circuit lines 46 provided along the Y direction of the TFT array substrate 20 are: a low-potential power supply line 70 as a trunk line, a first clock line 72 as trunk line, a second clock line 74 as a trunk line, and an initialization line 76 as a trunk line.
Note that these four lines, i.e. the low-potential power supply line 70, the first clock line 72, the second clock line 74, and the initialization line 76 are all provided between the gate driving circuit 60 and the substrate end side 26, i.e. outside the gate driving circuits 60.
The gate driving circuit 60 includes a plurality of stages ST that are connected to each other in a cascaded manner and sequentially output gate signals to the gate lines 42. Note that the stages ST are connected to the gate lines (not shown) on a one-to-one basis. Specifically, the stages ST are connected to each other in a cascaded manner. For example, a set terminal (not shown) in a j-th stage ST (j) receives a carry output from the preceding stage ST (j−1), and a reset terminal (not shown) receives a gate output from the subsequent stage ST (j+1).
The gate driving circuit lines 46 and the gate driving circuit 60 are electrically connected to each other through branch lines 78 extending in a lateral direction (X direction).
The following will describe more details of the gate driving circuit 60.
Each of the stages ST making up the gate driving circuit 60 includes TFT elements T1 through T13 and T15.
For example, in the stage ST (j−1) in the (j−1)th row, the TFT element T4 is placed on the upper side so as to be close to the preceding stage ST (j−2) and receives the carry signal from the preceding stage ST (j−2).
The TFT elements T1, T7, T10, T12, and T15 are placed along the branch line 78 as a connection line to the first clock line 72 and receive clock signals from the first clock line 72.
The TFT elements T11 and T5 are placed along the branch line 78 as a connection line to the second clock line 74 and receive clock signals from the second clock line 74.
The TFT element T6 is placed along the branch line 78 as a connection line to the initialization line 76 and receives an initialization signal from the initialization line 76.
The TFT elements T2, T3, T8, T9, and T13 are placed along the branch line 78 as a connection line to the low-potential power supply line 70 and receive low-potential signals for turning off gates of the TFT elements from the low-potential power supply line 70.